1. Field of the Invention
The invention, in general, relates to a method of making a three-dimensional integrated circuit and, more particularly, to a method providing high system yields in the fabrication of three-dimensional integrated circuits.
As used herein, the term three-dimensional integration is intended to connote the vertical interconnection of devices fabricated by planar technology. The advantages of a three-dimensionally integrated microelectronic system are, among others, that with substantially identical design rules, higher package densities and switching rates may be obtained as compared to two-dimensional systems. This is the result of shorter wiring paths or interconnections between individual devices or circuits and of the possibility of parallel data processing. The increased efficiency of the system is optimized by utilizing interconnection technology offering vertical interconnections which are freely selectable as to their positioning and which are suitable for very large-scale integration (VLSI).
2. The Prior Art
The following methods of fabricating three-dimensional circuit arrangements with freely selectable vertical contacts are known:
Y. Akasaka, Proc. IEEE 74 (1986), p. 1703, suggests depositing and recrystallizing polycrystalline silicon on a fully processed device layer so that further devices may be formed in the recrystallized layer. The disadvantages of such a method reside in the yield-reducing degradation of the devices in the lower level because of the high thermic stress induced by the recrystallization process and because of the necessarily serial processing of the overall system. They lead to correspondingly long cycle times during fabrication as well as to reduced yields because of accumulating process-inherent rejects. Both increase manufacturing costs significantly as compared to processing individual layers in separate substrates.
Y. Hayashi et al., Proc. 8th Int. Workshop on Future Electron Devices, 1990, page 85, proposes initial fabrication of separate device in separate substrates. Thereafter the substrates are reduced in their thickness to a few micrometers, provided with front and back leads and connected to each other by a bonding process. Special processes such as MOS-incompatible materials, for instance, gold, and patterning or structuring the back surface of the substrate, not provided for in standard fabrication techniques of semiconductors such as, for instance, complementary metal oxide semiconductors (CMOS) are, however, required to provide the front and back leads.
U.S. Pat. No. 4,939,568 describes a method of fabricating a three-dimensional integrated circuit structure by stacking individual ICs on a substrate to form a chip stack. To this end, a substrate provided with fully processed ICs is first divided into unit chips, whereby processing at the wafer level is completed. The chips are tested (wafer sorted), and a first unit chip is mounted on a substrate by thermocompression. Following this step, another chip is mounted (piggy-backed) in the same manner to the first chip. Hence, a first chip stack will be finished before fabrication of a further chip stack on another substrate can be begun. Further processing of the chip stack is, therefore, not possible at the wafer level.
A serious disadvantage of the aforementioned methods derives from the fact that equipment available in silicon technology lends itself only to processing of the discshaped or sliced substrates, known as wafers. Processing of substrates differing therefrom, especially of individual chips, can be performed with experimental test equipment only; but it is not possible on an industrial fabrication scale with its required high yields.
U.S. Pat. No. 4,954,875 describes a method of three-dimensional integration by stacking individual wafers, in which the interconnection between individual device planes is provided by specially formed vias. By combining substrates containing a plurality of identical devices, viz.: chips, the resulting yield of a multi-layer system is derived from the product of the individual yields. This leads to a drastically reduced yield in a system including several device planes, such as a system made in accordance with the method of U.S. Pat. No. 4,954,875. Thus, at a yield of 80% of an individual plane, the resulting total yield of a system combined of ten layers is but 10%, making such a system uneconomical. Accordingly, such technology is restricted to a few specialized applications. The yield of a device substrate is also dependant upon its circuit species and its fabrication process. Very high yields are obtained, for example, in the field of memory components, whereas markedly lower yields are obtained in logic devices, such as microprocessors. Particularly where different species of such circuits are stacked together, the total yield is disproportionately determined by that species of circuit providing the lowest yield.